The present invention relates to digital electrical circuits and, more particularly, to multi-stage buffers, for example, as used for integrated output circuits. A major objective of the present invention is to provide an integrated circuit output buffer which limits output switching noise when heavy output loads are connected, while optimizing throughput under light-load conditions.
Much of modern technological progress is identified with the development of integrated circuits, which provide high levels of functionality in a small space and require relatively small amounts of power. Most of these integrated circuits contain a large number of transistor switches which cause voltage fluctuations between high and low voltage levels which can represent alternate logic levels. A very large scale integration (VLSI) circuit can contain millions of such switching transistors.
One of the problems an integrated circuit designer must consider is noise. Each time a transistor turns on or off, transients are introduced in the signal and power lines associated with that transistor. A transient introduced into the power and ground lines affects other transistors coupled to the same power and ground lines. Where the affect is strong enough, the transients can introduce errors in data signals and even damage circuit components.
In particular, large current transients can be introduced by output buffers drive very large current or capacitive loads. In some cases, e.g., a read/write contention, an external device can drive an output buffer to the polarity opposite required by the data the buffer is driving, generating very high currents. High currents can also be generated when the output is shorted to a power source (V.sub.cc, V.sub.ss).
The deleterious affects of transients can be minimized by ensuring that sufficient current-carrying capacity is available in the power and ground lines and by adjusting the timing of circuit components to preclude multiple simultaneous switching which would exceed the capacity of associated power and ground lines. For most of the transistors in an integrated circuit, this design task is relatively straightforward since the power requirements are small and the loads imposed by neighboring circuit elements are predeterminable.
The design problem is more serious for the circuit components, like output buffers, which interface more or less directly to electrical components off the integrated circuit. The power requirements for interface components are usually much higher than for internal components because longer signal distances are involved. Furthermore, due to the wide applicability of many types of integrated circuits, e.g., microprocessors and memory components, a wide range of interfacing components or loads must be provided for. In addition, since it is never certain that an incorporating system will operate as intended, these components should be able to withstand at least some "prohibited conditions", such as a read/write contention.
Typically, integrated circuits incorporate output buffers designed to accommodate the higher and more uncertain load requirements for interface components. Output buffers use large current sources to overcome large and non-predetermined loads. Since output buffers switch large currents on and off, they introduce relatively large transients in the incorporating integrated circuit. Some integrated circuits use time-staggered output buffers to limit the number of transients occurring at any given moment. While staggering can minimize the effect of cumulative transients, individual transients can be quite substantial.
U.S. Pat. No. 4,782,252 to Levy et al. discloses a buffer with a variable resistive device for limiting the transients introduced by turning on a buffer transistor. Alternatively, a delay can be introduced between activations of successive stages of an multi-stage buffer so that transient power is distributed over time.
The foregoing approaches to avoiding buffer transients involve a compromise. Longer delays improve transient handling but impair device throughput. If a long delay is selected for managing transients where large maximum loads are anticipated, throughput will be unnecessarily slow when the device is incorporated in a system imposing small loads but requiring high speed. If short delays are selected, a large load can induce a transient that would result in an error or circuit damage.
Moreover, while the forgoing staggered transition approaches buffer the transition to data, they do not buffer the return to the high-impedance state. Normally, a high-impedance state is provided between successive read events. Thus, noise is generated every read cycle upon the return to the high-impedance state, even though the transition to data is buffered.
What is needed is a buffer which can minimize transients while providing higher speeds when lower external loads are to be driven. In addition, buffering is required for both the transition to data and the transition to the high-impedance state.